1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a technique of reducing the layout area of elements for fixing the potentials of wells in a semiconductor device.
2. Description of the Background Art
In a semiconductor integrated circuit, it is important to optimize the electric characteristics of individual elements and reduce the width of spaces between the elements, in order to improve the performance of and refine the integrated circuit. In general, a MOSFET is formed on a well prepared by doping a surface of a semiconductor substrate with an impurity. For example, an N-type MOSFET (hereinafter also referred to as xe2x80x9cNMOSFETxe2x80x9d) is formed on a P-type well (hereinafter also referred to as xe2x80x9cP wellxe2x80x9d).
In this case, a plurality of types of NMOSFETs having different transistor characteristics can be formed on the same semiconductor substrate by adjusting only impurity profiles of portions close to surfaces of P wells or regions shallower than an element isolation insulator film (hereinafter also referred to as xe2x80x9celement isolation filmxe2x80x9d). Alternatively, the characteristics of NMOSFETs formed on the same substrate can be made different from each other by adjusting impurity profiles of deeper regions, in order to optimize the electric characteristics of the elements. In other words, a plurality of types of P wells having different impurity profiles are prepared for forming NMOSFETs different in characteristic and application from each other on the P wells respectively.
FIG. 22 is a sectional view of a conventional semiconductor device 1P, and FIG. 23 is a typical plan view or layout diagram for illustrating a part of the semiconductor device 1P. In the semiconductor device 1P, P wells 11P and 12P having different impurity profiles are formed in a surface 50SP of a semiconductor substrate (hereinafter also referred to as xe2x80x9csubstratexe2x80x9d) 50P. In particular, an element isolation film 51BP is formed at the boundary between the wells 11P and 12P in the conventional semiconductor device 1P.
An NMOSFET 91P is formed on the P well 11P, and a P-type semiconductor layer (hereinafter also referred to as xe2x80x9cP-type layerxe2x80x9d) 21P for fixing the potential of the P well 11P is formed in the P well 11P. Similarly, an NMOSFET 92P different in characteristic from the aforementioned NMOSFET 91P is formed on the P well 12P, and a P-type layer 22P for fixing the potential of the P well 12P is formed in the P well 12P. While the P-type layers 21P and 22P are formed in the vicinity of the boundary between the P wells 11P and 12P in FIG. 22, the P-type layers 21P and 22P may alternatively be formed on other portions in the P wells 11P and 12P respectively. Element isolation films 51P and 51BP isolate the NMOSFETs 91P and 92P and the P-type layers 21P and 22P from each other.
The P-type layers 21P and 22P are connected to a wire 40P through contacts 31P and 32P provided in contact holes 70H1P and 70H2P formed in an interlayer isolation film 70P respectively. The wire 40P is connected to a prescribed potential, thereby fixing the P wells 11P and 12P to the prescribed potential through the contacts 31P and 32P and the P-type layers 21P and 22P.
Source/drain regions 61P of the NMOSFETs 91P and 92P are formed in the surface 50SP, and gate insulator films 63P (see FIG. 26) and gate electrodes 62P are successively formed on the surface 50SP. The source/drain regions 61P are connected to wires 66P through contacts 65P provided in contact holes 70HP formed in the interlayer isolation film 70P.
FIGS. 24 to 29 are sectional views for illustrating a method of manufacturing the semiconductor device 1P. The method of manufacturing the semiconductor device 1P is now described with reference to these drawings.
First, the element isolation films 51P and 51BP are formed in the surface 50SP of the substrate 50P for separating regions for forming the NMOSFETs 91P and 92P and the P-type layers 21P and 22P from each other.
Then, a resist film 81P is arranged on the surface 50SP while opening a region for forming the P well 12P for ion-implanting a P-type impurity into the surface 50SP through the resist film 81P serving as a mask (see FIG. 24). More specifically, boron is implanted, for example, under conditions of 300 keV to 1.5 MeV and 1xc3x971012 to 1xc3x971014/cm2 for forming a retrograde well, under implantation conditions of 80 keV to 160 keV and 1xc3x971012 to 5xc3x971013/cm2 for a channel-cut layer, and under implantation conditions of 15 keV to 70 keV and 3xc3x971012 to 5xc3x971013/cm2 for a threshold control layer, thereby forming the P well 12P consisting of the retrograde well, channel-cut layer and threshold control layer.
Then, a resist film 82P is arranged on the surface 50SP while opening a region for forming the P well 11P for ion-implanting a P-type impurity into the surface 50SP through the resist film 82P serving as a mask (see FIG. 25). More specifically, boron is implanted, for example, under conditions of 200 keV to 500 keV and 5xc3x971012 to 1xc3x971014/cm2 for forming a retrograde well, under implantation conditions of 80 keV to 160 keV and 3xc3x971012 to 2xc3x971013/cm2 for a channel-cut layer, and under implantation conditions of 15 keV to 70 keV and 5xc3x971012 to 1xc3x971014/cm2 for a threshold control layer, thereby forming the P well 11P consisting of the retrograde well, channel-cut layer and threshold control layer.
Thereafter N-type wells are formed in regions for forming NMOSFETs (not shown).
Thereafter films for the gate insulator films 63P and the gate electrodes 62P are formed and patterned into prescribed shapes, thereby forming the gate insulator films 63P and the gate electrodes 62P (see FIG. 26). N-type extension layers 69P are formed at the source/drain regions of the NMOSFETs, and P-type extension layers are formed at source/drain regions of the PMOSFETs (see FIG. 27). While P-type extension layers 29P are formed in regions for forming the P-type layers 21P an 22P, formation of such extension layers 29P may be omitted. Thereafter an insulator film is formed to entirely cover the surface 50SP and anisotropically etched thereby forming side-wall-spacers (hereinafter also referred to as xe2x80x9cspacersxe2x80x9d) 64P.
Then, a resist film 83P is arranged on the surface 50SP while opening regions for forming the NMOSFETs 91P and 92P and regions for forming N-type layers for fixing the potentials of the N wells (not shown) for ion-implanting an N-type impurity into the surface 50SP through the resist film 83P serving as a mask (see FIG. 28). For example, arsenic is implanted under conditions of 5 keV to 100 keV and 1xc3x971015 to 6xc3x97105/cm2, thereby forming the source/drain regions 61P of the NMOSFETs 91P and 92P and the aforementioned N-type layers.
Then, a resist film 84P is arranged on the surface 50SP while opening regions for forming the P-type layers 21P and 22P and the PMOSFETs for ion-implanting a P-type impurity into the surface 50SP through the resist film 84P serving as a mask (see FIG. 29). For example, boron is implanted under conditions of 1 keV to 20 keV and 1xc3x971015 to 6xc3x971015/cm2, thereby forming the P-type layers 21P and 22P and the source/drain regions of the PMOSFETs.
Then, the interlayer isolation film 70P is formed entirely over the surface 50S to cover the gate electrodes 62P etc., and the contact holes 70HP, 70H1P and 70H2P are formed in prescribed positions respectively. A conductive material such as a metal or polysilicon is deposited to cover the overall surface of the interlayer isolation film 70P, thereby forming the contacts 31P, 32P and 65P and the wires 40P and 66P. The semiconductor device 1P shown in FIG. 22 is completed through the aforementioned steps. A plurality of wiring layers are formed at need for manufacturing an LSI.
When the masks etc. are misaligned in the photolithography steps (see FIGS. 24 and 25) for forming the wells 11P and 12P respectively, the P wells 11P and 12P may be separated from each other (see a sectional view shown in FIG. 30). Also in this case, the P wells 11P and 12P can be fixed to a prescribed potential since the P-type layers 21P and 22P and the contacts 31P and 32P are provided for the P wells 11P and 12P respectively.
Also when the wells 11P and 12P are enclosed with a bottom N well 13P and an N well 14P as shown in a sectional view of FIG. 31 and a plan view of FIG. 32, the P wells 11P and 12P may be separated from each other. If the P wells 11P and 12P are not electrically connected with each other, the potentials of the P wells 11P and 12P tend to float. Also in the semiconductor device having the aforementioned bottom N well 13P and the N well 14P, therefore, the P-type layers 21P and 22P and the contacts 31P and 32P are provided for the P wells 11P and 12P respectively.
In the conventional semiconductor device 1P or the like, the element isolation film 51P separates the regions for forming the MOSFETs from each other while the element isolation film 51BP is also formed at the boundary between the P wells 11P and 12P, and hence diffusion layers for fixing the potentials of the wells, the contacts and the wires must be provided for the respective wells. Therefore, the ratio of regions for forming the aforementioned diffusion layers etc. is disadvantageously increased in the overall semiconductor device. Particularly when the P-type layers 21P and 22P of the wells 11P and 12P are not arranged in proximity to each other, the layout area for the wire 40P increases the aforementioned ratio.
According to a first aspect of the present invention, a semiconductor device comprises a semiconductor substrate, a first well of a prescribed conductivity type selectively formed in a surface of the semiconductor substrate, a second well of the same conductivity type as the prescribed conductivity type selectively formed in the surface of the semiconductor substrate, a first conductive layer, which is formed by lowering the resistivity of the surface, across the first well and the second well in the surface of the semiconductor substrate with an end provided on the first well and another end provided on the second well and a first contact electrically connected with the first well.
According the first aspect, the first well and the second well are electrically connected with each other through the first conductive layer, whereby the potential of the second well can be fixed by fixing the potential of the first well through the first contact. In other words, the potentials of the first and second wells can be simultaneously fixed by the first contact. In this case, the potential of the second well can be stably fixed through the first conductive layer regardless of contact/non-contact between the first and second wells.
According to this aspect, further, there is no need to provide conductive layers and contacts for the first well and the second well respectively. As compared with the conventional semiconductor device provided with the conductive layers and the contacts for the first well and the second well respectively, therefore, the layout area of elements for fixing the potentials of the first well and the second well can be reduced. In particular, the aforementioned layout area can be remarkably reduced by so providing the first conductive layer as to connect the adjacent first and second wells at the minimum distance. Thus, the overall size of the semiconductor device (or chip) can be so reduced that the number of semiconductor devices obtainable from a unit wafer is increased and the cost can be reduced.
In this case, wires other than those for fixing the potentials of the first and second wells can be arranged in the vicinity of the first conductive layer by bringing only the first contact into contact with the first conductive layer. In other words, the degree of freedom in layout is improved as compared with the case of providing a plurality of contacts in contact with the first conductive layer.
According to a second aspect of the present invention, the first contact is in contact with the first conductive layer.
According to the second aspect, the first contact can be reliably electrically connected with the first well through the first conductive layer, whereby the potentials of the first and second wells can be stably fixed.
According to a third aspect of the present invention, the semiconductor device further comprises a second contact in contact with the first conductive layer.
According to the third aspect, the total resistance of the contacts for fixing the potentials of the first and second wells can be reduced as compared with the case provided with only the first contact.
According to a fourth aspect of the present invention, the first contact is arranged in opposition to the first well through the first conductive layer while the second contact is arranged in opposition to the second well through the first conductive layer.
According to the fourth aspect, the first contact is in proximity to the first well through the first conductive layer and the second contact is in proximity to the second well through the second conductive layer. Thus, the potential of the first well can be more stably fixed through the first contact, and the potential of the second well can be more stably fixed through the second contact.
According to a fifth aspect of the present invention, the semiconductor device further comprises a second conductive layer formed in the surface of the semiconductor substrate by lowering the resistivity of the surface and provided on the first well without being in contact with the second well, and the first contact is in contact with the second conductive layer.
According to the fifth aspect, the first contact and the first well can be reliably electrically connected with each other through the second conductive layer, whereby the potential of the first well can be stably fixed. In this case, the potential of the second well can be stably fixed through the first conductive layer regardless of contact/non-contact between the first and second wells.
In this case, it is possible to eliminate necessity of providing a contact for the first conductive layer. Therefore, the layout area of the first conductive layer can be reduced as compared with the case of providing a contact for the first conductive layer, whereby miniaturization of the semiconductor device, increase of the number of semiconductor devices obtainable from a unit wafer and reduction of the cost can be attained. Further, it is not at all necessary to provide a wire for a contact connected with the first conductive layer in the vicinity of the first conductive layer, whereby another wire can be arranged in the vicinity of the first conductive layer. In other words, the degree of freedom in layout is further improved.
According to a sixth aspect of the present invention, the first conductive layer includes at least one of an impurity introduction layer of the same conductivity type as the prescribed conductivity type and a compound layer of the material for the semiconductor substrate and a metal.
According to the sixth aspect, the first conductive layer can be reliably supplied with conductivity. In particular, the resistivity of the first conductive layer can be remarkably reduced due to the compound layer, and the potentials of the first and second wells can be more stably fixed as compared with the case of the first conductive layer consisting of only the impurity introduction layer.
According to a seventh aspect of the present invention, the first conductive layer has lower resistivity than the first well and the second well.
According to the seventh aspect, the wells and the contact can be excellently brought into ohmic contact with each other.
According to an eighth aspect of the present invention, the second conductive layer includes at least one of an impurity introduction layer of the same conductivity type as the prescribed conductivity type and a compound layer of the material for the semiconductor substrate and a metal.
According to the eighth aspect, the second conductive layer can be reliably supplied with conductivity. In particular, the resistivity of the second conductive layer can be remarkably reduced due to the compound layer, and the potentials of the first and second wells can be more stably fixed as compared with the case of the second conductivity layer consisting of only the impurity introduction layer.
According to a ninth aspect of the present invention, the second conductive layer has lower resistivity than the first well.
According to the ninth aspect, the wells and the contact can be excellently brought into ohmic contact with each other.
According to a tenth aspect of the present invention, the first well and the second well have different impurity profiles.
According to the tenth aspect, the first and second wells having different impurity profiles are generally formed through different steps with different masks. Also when misalignment results from employment of different masks and the first and second wells are not in contact with each other, any of the aforementioned effects according to the first to ninth aspects can be attained.
An object of the present invention is to provide a semiconductor device capable of stably fixing the potentials of wells and reduced in layout area of elements for fixing the potentials.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.